The present invention relates to a data receiving apparatus, a data receiving method, and a non-transitory computer readable medium storing a program that are preferably used for serial communication, especially for high-speed serial communication. More specifically, the present invention relates to a data receiving apparatus, a data receiving method, and a non-transitory computer readable medium storing a program that transmit and receive data scrambled in a transmission side and descrambled in a reception side.
In high-speed serial communication, scramble processing is performed on data to be transmitted in order to prevent periodicity of data (continuation of data of the same pattern). Therefore, descramble processing is performed on data that is received.
Japanese Unexamined Patent Application Publication No. 2005-268910 discloses a data receiving apparatus related to the present invention. In the data receiving apparatus according to Japanese Unexamined Patent Application Publication No. 2005-268910, initialization of a descrambling circuit can be performed even when a part of an initialization symbol including a COM symbol or timing adjusting data including an SKP symbol is corrupted due to the influence of noise on a transmission line. Description will be made hereinafter by taking a PCI Express bus system as an example.
FIG. 24 shows a data transfer apparatus disclosed in Japanese Unexamined Patent Application Publication No. 2005-268910. As shown in FIG. 24, a scrambling circuit 501 scrambles data to be transmitted. An 8B/10B encoder 502 encodes 8-bit data that is scrambled to 10-bit data in which data of “0” or “1” does not continue for predetermined times or more. A parallel/serial (P/S) converter 503 converts parallel data into serial data. A Tx 504 is a sending transmission line (lane) of differential form. A data transmitting apparatus is thus formed. An Rx 505 is a receiving transmission line of differential form. A serial/parallel (S/P) converter 506 converts reception data from serial data into parallel data. An elastic buffer 507 is a buffer circuit that adjusts deviations of clock frequencies between the transmission side and the reception side. An 8B/10B decoder 508 decodes 10-bit data into 8-bit data. An SKP/COM converter 509 is a symbol converter that converts SKP symbols into COM symbols. A descrambling circuit 510 descrambles reception data. A data receiving apparatus is thus formed.
The scrambling circuit 501 scrambles the transmission data. Further, the 8B/10B encoder 502 encodes 8-bit data to 10-bit data so that data of “0” or “1” does not continue for predetermined times or more. Then the P/S converter 503 converts parallel data into serial data, and transmits the serial data to the sending transmission line (lane) of differential form 504. Note that clocks are embedded in data signals. Further, the data received from the receiving transmission line (lane) of differential form 505 is converted from the serial data into the parallel data by the S/P converter 506. Then, the elastic buffer circuit 507 corrects deviations of clock frequencies between the transmission side and the reception side, the 8B/10B decoder 508 decodes 10-bit data into 8-bit data, the SKP/COM converter 509 converts all the SKP symbols in an SKP ordered set into COM symbols, and the descrambling circuit 510 descrambles the data.
In such a PCI Express bus system, each of the scramble processing by the scrambling circuit 501 and the descramble processing by the descrambling circuit 510 is executed by a circuit using a linear feedback shift register (LFSR) shown in FIG. 25. In FIG. 25, S0 to S15, and D0 to D7 denote shift registers, and X1˜X4 denote EXOR circuits. The scrambling here is indicated by the following polynomial expression.G(X)=X16+X5+X4+X3+1
Rules shown below are applied to the scrambling circuit 501 and the descrambling circuit 510.
(1) Shift registers are initialized to an initial value (hFFFF) in COM symbols.
(2) Shift registers are shifted by 8 bits in other symbols than SKP symbols (shift registers are not shifted in SKP symbols).
(3) Scramble processing is performed in all D codes except a training sequence and a compliance pattern.
(4) Scrambling is not performed in all K codes.
The COM symbol here denotes data or an initializing symbol for initializing the scrambling circuit 501 and the descrambling circuit 510. Further, the SKP symbol denotes timing adjusting data to correct deviations of clock frequencies between the transmission side and the reception side without shifting the LFSRs of the scrambling circuit 501 and the descrambling circuit 510. Further, the K code is 12 kinds of special data other than normal data, and includes the above COM symbols and SKP symbols. Meanwhile, the D code denotes a data symbol other than controlling data such as the K code.
In the PCI Express bus system, a timing adjusting data set (SKP ordered set) is inserted at predetermined intervals (for each of 1080 to 1156 symbols) when data transfer becomes Idle (D0.0, i.e., when 00h of D code is transmitted) in order to absorb deviations of the clock frequencies between the transmission side and the reception side. As shown in FIG. 26A, this SKP ordered set includes one COM symbol and the following three SKP symbols.
In the elastic buffer circuit 507, SKP symbols are inserted as shown in FIG. 26B when the elastic buffer circuit 507 may generate underflow, and the number of SKP symbols is decreased as shown in FIG. 26C when the elastic buffer circuit 507 may generate overflow, thereby adjusting deviations of clock frequencies between the transmission side and the reception side.
In this way, the shift registers in the descrambling circuit 510 are set so as not to be shifted in the SKP symbols so that the SKP symbols after passing through the elastic buffer circuit 507 do not have a bad effect on normal data. Further, since the SKP ordered set definitely includes a COM symbol first, the shift registers are always in a state of an initial value at the position of the SKP symbols.
In Japanese Unexamined Patent Application Publication No. 2005-268910, the SKP/COM converter 509 replaces the SKP symbols in a data sequence after passing through the elastic buffer circuit 507 with COM symbols. FIGS. 27A, 27B, and 27C are diagrams for describing data input to the descrambling circuit 510 of the data receiving apparatus disclosed in Japanese Unexamined Patent Application Publication No. 2005-268910. It is assumed that an error is occurred in the first SKP symbol in an SKP ordered set, for example, as shown in FIG. 27B in a communication path or the like in data generated as shown in FIG. 27A. In such a case, according to the data receiving apparatus disclosed in Japanese Unexamined Patent Application Publication No. 2005-268910, as shown in FIG. 27C, all the SKP symbols are replaced with COM symbols before descrambling is performed. Therefore, the descrambling circuit 510 repeats initialization a plurality of times corresponding to the number of COM symbols that are replaced even when there is an error in the SKP symbol. Accordingly, the initialization is definitely performed, which makes it possible to definitely associate the descramble processing in the reception side with the scramble processing in the transmission side.